x86-64 Cheat Sheet

General-Purpose Registers

Name64-bit32-bit16-bit8-bitPreservedUsage
Accumulator raxeaxaxah:al return
Base rbxebxbxbh:bl
Counter rcxecxcxch:cl arg4
Data rdxedxdxdh:dl arg3
Source rsiesisisil arg2
Destination rdiedididil arg1
r8r8dr8wr8b arg5
r9r9dr9wr9b arg6
r10r10dr10wr10b
r11r11dr11wr11b
r12r12dr12wr12b
r13r13dr13wr13b
r14r14dr14wr14b
r15r15dr15wr15b
Base Pointer rbpebpbpbpl function stack base (optional)
Stack Pointer rspespspspl top of stack *
Instruction Pointer ripeipip

* The rsp register must be 16-byte aligned (i.e. divisible by 16) before making a call.

Flags

LabelNameDescription
CFcarry flaglast arithmetic operation carried/borrowed
ZFzero flagresult of last operation was zero
SFsign flagresult of last operation was negative
OFoverflow flaglast result had a signed overflow

Jumps

InstructionTestAfter TEST x, xAfter CMP y, x
jeZFx = 0x = y
jne~ZFx ≠ 0x ≠ y
ja~CF & ~ZFx > y (unsigned)
jae~CFx ≥ y (unsigned)
jbCFx < y (unsigned)
jbeCF | ZFx ≤ y (unsigned)
jg~ZF & SF=OFx > 0 (signed)x > y (signed)
jgeSF=OFx ≥ 0 (signed)x ≥ y (signed)
jlSF≠OFx < 0 (signed)x < y (signed)
jleZF | SF≠OFx ≤ 0 (signed)x ≤ y (signed)
jcCF
jnc~CF
joOF
jno~OF
jsSF
jns~SF

Floating Point

Floating point registers st(0) to st(7) are manipulated by the x87 instructions, which we won't be using.

SIMD: MMX, SSE, AVX

We will be using these registers and the instructions that work on them for floating point operations:

512-bit256-bit128-bitPreservedUsage
zmm0ymm0xmm0 arg1, return
zmm1ymm1xmm1 arg2
zmm7ymm7xmm7 arg8
zmm8ymm8xmm8
zmm15ymm15xmm15

Addressing

Memory access in an instruction: displacement(base, index, scale)

e.g. -16(%rbp, %rdx, 8) == rbp + (rdx * 8) - 16. In C, that might be rbp[rdx-2] if you're working with elements of 8 bytes.

Operand Size

NameSizeSuffixData
byte8-bitsb.byte
word16-bitsw.word
long word32-bitsl.long
quad word64-bitsq.quad

Instructions


References: Intel 64 and IA-32 Architectures Software Developer’s Manuals; System V Application Binary Interface: AMD64 Architecture Processor Supplement.